1. Field of the Invention
This invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In some known semiconductor devices having a plurality of semiconductor chips stacked to realize high functionality, a configuration is employed in which upper and lower semiconductor chips are electrically connected by way of through silicon vias (hereafter, abbreviated as “TSV”) which are formed to penetrate through the semiconductor chips. In particular, a process (via-last process) is known in which circuit elements, wirings, surface electrodes and the like are formed on the major surface of a substrate and then through silicon vias are formed from the rear surface of the substrate.
In such a configuration or process, an annular insulating isolation portion (insulating ring) may be provided to surround each of the through silicon vias for the purposes of insulation between the through silicon via and an element region, reduction of parasitic capacity between the through silicon vias, and/or prevention of diffusion of a metal material forming the through silicon vias to the element region.
For example, Japanese Laid-Open Patent Publication No. 2010-232400 (Patent Document 1) discloses a process to realize a through silicon via having a structure in which a wiring penetrates through a substrate from one surface to the other by forming a circuit element and a first wiring layer on the top surface of a semiconductor substrate, then forming a through hole in the rear surface thereof, and forming a second wiring layer in the through hole after the inner wall of the through hole is covered with an insulating layer. An annular insulating ring surrounding the through silicon via is realized by covering the inner wall of the through silicon via with an insulating film before forming the second wiring layer (see FIG. 3 of Patent Document 1).